Flash memory is a type of electronic memory media that can hold its data in the absence of operating power. Flash memory can be programmed, erased, and reprogrammed during its useful life (which may be up to one million write cycles for typical flash memory devices). Flash memory is becoming increasingly popular as a reliable, compact, and inexpensive nonvolatile memory in a number of consumer, commercial, and other applications. As electronic devices get smaller and smaller, it becomes desirable to increase the amount of data that can be stored per unit area on an integrated circuit memory cell, such as a flash memory unit.
One conventional flash memory technology is based upon a memory cell that utilizes a charge trapping dielectric cell that is capable of storing two bits of data. One example of this type of non-volatile memory device is known as a dual-bit Flash electrically erasable and programmable read-only memory (EEPROM), which is available under the trademark MIRRORBIT™ from Spansion, Inc., Sunnyvale, Calif. Such dual-bit memory cells utilize a single silicon nitride layer having two separate charge storage regions to store charge within the silicon nitride layer. In such an arrangement, one bit can be stored using a first charge storing region on one side of the silicon nitride layer, while a second bit can be stored using a second charge storing region on the other side of the same silicon nitride layer. For example, a left bit and right bit can be stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell, respectively. In comparison to a conventional EEPROM cell, a dual-bit memory cell can store twice as much information in a memory array of equal size.
FIG. 1 is a cross-sectional view of a conventional dual-bit memory cell 50. The memory cell 50 has a dual-bit (bit1, bit2) architecture that allows twice as much storage capacity as a conventional EEPROM memory device.
The conventional memory cell 50 includes a substrate 54, a first insulator layer 62 disposed over the substrate 54, a nitride charge storage layer 64 disposed over the first insulator layer 62, a second insulator layer 66 disposed over the charge storage layer 64, and a polysilicon control gate 68 disposed over the second insulator layer 66. To produce an operable memory device, a first metal silicide contact (not shown) can be disposed on substrate 54, and the control gate 66 can be capped with a second metal silicide contact (not shown).
In one implementation, the substrate 54 is a P-type semiconductor substrate 54 having a first buried junction region 60 and a second buried junction region 61 formed within substrate 54 in self-alignment with the memory cell 50. First buried junction region 60 and second buried junction region 61 are each formed from an N+ semiconductor material. The first insulator layer 62, the charge storage layer 64, and the second insulator layer 66 can be implemented using an oxide-nitride-oxide (ONO) configuration in which a nitride charge storage layer 64 is sandwiched between two silicon dioxide insulator layers 62, 66. Alternatively, charge storage layer 64 may utilize buried polysilicon islands as a charge trapping layer. The charge storage layer 64 is capable of holding a charge.
Memory cell 50 can store two data bits: a left bit represented by the circle (bit 1); and a right bit represented by the circle (bit 2). In practice, memory cell 50 is generally symmetrical, thus first buried junction region 60 and second buried junction region 61 are interchangeable. In this regard, first buried junction region 60 may serve as the source region with respect to the right bit (bit 2), while second buried junction region 61 may serve as the drain region with respect to the right bit (bit 2). Conversely, second buried junction region 61 may serve as the source region with respect to the left bit (bit 1), while first buried junction region 60 may serve as the drain region with respect to the left bit (bit 1). A threshold voltage exists between the control gate 66 and the substrate 54 to prevent leakage during functioning of the device.
While a single dual-bit memory cell 50 is illustrated in FIG. 1, it will be appreciated that any suitable number of the dual-bit memory cells 50 could be used to form a memory array, as described below with reference to FIG. 2.
FIG. 2 is a simplified diagram of a plurality of dual-bit memory cells arranged in accordance with a conventional array architecture 200 (a practical array architecture can include thousands of dual-bit memory cells 50). Array architecture 200 includes a number of buried bit lines formed in a semiconductor substrate as mentioned above. FIG. 2 depicts three buried bit lines (BLs) 202, 204, and 206, each being capable of functioning as a drain or a source for memory cells in array architecture 200. Array architecture 200 also includes a number of word lines (WLs) correspond to the gate of the memory cells and are utilized to control the gate voltage of the memory cells. FIG. 2 depicts four WLs 208, 210, 212, and 214 that generally form a crisscross pattern with the bit lines. Although not shown in FIG. 2, charge storage layer, such as an ONO stack, resides between the BLs and the WLs. The dashed line circles in FIG. 2 represent two of the dual-bit memory cells in array architecture 200. Notably, BL 204 is shared by the dual-bit memory cells. Array architecture 200 is known as a virtual ground architecture because ground potential can be applied to any selected BL and there need not be any BLs with a fixed ground potential.
Control logic and circuitry (not shown) for array architecture 200 governs the selection of memory cells, the application of voltage to the WLs 208, 210, 212, 214, and the application of voltage to the BLs 202, 204, 206 during conventional flash memory operations, such as: programming; reading; erasing; and soft programming. Voltage is delivered to the BLs 202, 204, 206 using BL contacts 230. FIG. 2 depicts three conductive metal lines 220, 222, and 224 and three BL contacts 230. For a given BL 202, 204, 206, a BL contact is used once every 16 WLs because the resistance of the BLs 202, 204, 206 is very high.
FIG. 3 shows an array 300 of dual-bit memory cells comprising a number of core array sectors 320-350. Each of the core array sectors 320-350 comprises a number of BLs and WLs which form the dual bit memory cells as described in FIG. 2. Each core array sector 320-350 can be erased by selecting that particular sector for erasure, and applying appropriate voltages to a common P-well (not shown) in the substrate, BLs and WLs in the selected sector. To select a particular core array sector 320-350 to be erased, each of the core array sectors 320-350 has its own corresponding sector select transistor 310A-310D.
FIG. 4 shows an array 400 of dual-bit memory cells and the biasing used during a hot hole erase operation to erase a selected sector in the array 400. The array 400 of dual-bit memory cells comprises a plurality of sectors. Each sector comprises a number of WLs 410, 420 and a number of BLs 430, 440. All of the sectors share a common P-well 405.
When a particular sector is selected to be erased via a hot hole erase operation, a sector select transistor for that sector can be used to pass the required BL voltage to that particular sector. The selected core array sector can then be erased by applying a negative bias voltage (−VG), for example minus nine volts, to each of the WLs 410 in the selected sector, applying a positive BL voltage (+VB), for example nine volts, to each of the BLs 430 in the selected sector, grounding each of the WLs 420 and BLs 440 in the unselected sectors 330-350 at zero volts, and grounding the common P-well 405 at zero volts.
In the hot hole erase operation of FIG. 4, individual sector select transistors 310A-310D are required for each core array sector 320-350 to prevent an erase disturbance. Since each sector 320-350 needs a dedicate sector select transistor, valuable die area is consumed. Moreover, the erase disturbance can occur to the unselected sector during a hot hole erase operation of the selected sector because the positive BL voltage (+VB) on the BLs can generate undesired hot holes and can erase of the unselected sectors. Applying a positive BL voltage (+VB) to the selected BLs 430 and grounding the unselected BLs 420 can be achieved by controlling the different sector select transistors 310A and 310B-D between the sectors 320-350 of FIG. 3.